1. Technical Field
The present disclosure relates to a method for multilevel programming of phase change memory cells and to a related phase change memory device.
2. Description of the Related Art
As is known, phase change memories use a class of materials having the property of switching between two phases having distinct electrical characteristics, associated with two different crystallographic structures: an amorphous, disorderly phase, and a crystalline or polycrystalline, orderly phase. The two phases are associated to resistivities of considerably different values.
Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, are exploited in phase change memory cells. A currently widely used chalcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), also called GST, which has been proposed for storing information on overwritable disks and for mass storage. In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
Phase changes are obtained by locally increasing the temperature. Below a temperature of 150° C., both phases are stable. Starting from an amorphous state, and raising the temperature above 200° C., there is a rapid nucleation of crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change to become crystalline. To bring the chalcogenide back to the amorphous state, the temperature is raised above the melting temperature (approximately 600° C.), and then a rapid cool off the chalcogenide is performed.
Memory devices exploiting the properties of chalcogenic material (also called phase change memory devices) have already been proposed.
As discussed in EP-A-1 326 254 (corresponding to US-A-2003/0185047) a memory element of a memory cell of a phase change memory device comprises a chalcogenic material and a resistive electrode, also called a heater (or “rapier”).
From an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the resistive electrode in contact or in close proximity with the chalcogenic material, and thus heating the chalcogenic material by the Joule effect. In particular, when the chalcogenic material is in the amorphous, high resistivity state (also called the “reset state”), one can apply a voltage/current pulse of a suitable length and amplitude (or a number of such pulses) and allow the chalcogenic material to cool slowly. In this condition, the chalcogenic material changes its state and switches from a high resistivity to a low resistivity state (also called the “set state”). Vice versa, when the chalcogenic material is in the set state, one can apply a voltage/current pulse of suitable length and high amplitude so as to cause the chalcogenic material to switch back to the amorphous phase.
An advantageous approach to programming of phase change memory cells, that is particularly aimed at multilevel programming, is described in US2008/151612. A common reset pulse of a predefined amplitude and energy (suitably determined by an electrical characterization) is supplied to the phase-change memory cells in order to form small volumes of amorphous material (so called “amorphous caps”) at an interface between respective phase change regions and heaters. Then, low-resistance crystalline conductive paths (or percolation paths), i.e., parallel current paths, are created through the high-resistance amorphous volumes of phase change material by providing appropriate sequences of set programming pulses, in order to program bits of the so called “parallel-type”. An average cross-section of the conductive paths (and hence the resistance of the related memory element and the programmed state thereof) are determined by controlling the width, amplitude and/or number of pulses in each sequence. Program and verify algorithms are used in order to determine when the read current in the memory cell reaches a desired level (indicative of a reached “programmed state”). In particular, the programming current is increased at predefined steps and programming is interrupted when a suitable cross-section of the conductive path is reached, generating the desired read current level.